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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 1998 (all rights reserved) cirrus logic, inc. crystal semiconductor products division p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.crystal.com cs5394 117 db, 48 khz audio a/d converter features l 24-bit conversion l complete cmos stereo a/d system delta-sigma a/d converters digital anti-alias filtering s/h circuitry and voltage reference l adjustable system sampling rates including 32 khz, 44.1 khz and 48 khz l 117 db dynamic range (a-weighted) l -103 db thd + n l differential analog circuitry l internal 64 oversampling l linear phase digital anti-alias filtering with >117 db stopband attenuation l single +5 v power supply l power down mode description the cs5394 is a complete analog-to-digital converter for stereo digital audio systems. it performs sampling, ana- log-to-digital conversion and anti-alias filtering, generating 24-bit values for both left and right inputs in serial form. the output sample rate can be up to 50 khz per channel. the cs5394 uses 7th-order, delta-sigma modulation with 64 oversampling followed by digital filtering and decimation, which removes the need for an external anti- alias filter. the adc uses a differential architecture which provides excellent noise rejection. the cs5394 has a linear phase filter with passband of dc to 22.1 khz, 0.005 db passband ripple and >117 db stopband rejection. the cs5394 is targeted for the highest performance pro- fessional audio systems requiring wide dynamic range, negligible distortion and low noise. ordering information cs5394-ks -10 to 70 c 28-pin soic CDB5394 evaluation board i voltage reference serial output interface digital filter high pass filter high pass filter decimation digital filter decimation lp filter dac - + - + s/h lp filter dac - + - + s/h ainr+ va sclk sdata mclkd pdn 14 16 20 19 24 27 vcom 2 mclka 7 lrck 13 adctl 6 lgnd 22 tsto1 8 ainr- 26 comparator comparator ainl+ 4 ainl- 5 vref 1 dfs 18 s/m 17 agnd 3 agnd 25 agnd 28 23 vl tsto2 21 vd 11 dgnd 12 calibration microcontroller cal 10 dactl 9 dgnd 15 may 98 ds258pp4
cs5394 2 ds258pp4 table of contents analog characteristics ........................................................................... 3 power and thermal characteristics .................................................. 4 digital filter characteristics ............................................................... 4 digital characteristics ............................................................................ 4 absolute maximum ratings ....................................................................... 5 recommended operating conditions ................................................... 5 switching characteristics ...................................................................... 6 general description .................................................................................. 9 system design ................................................................................................ 9 master clock ............................................................................................... 9 serial data interface ................................................................................ 9 serial data .................................................................................................. 9 serial clock ................................................................................................. 9 left / right clock ...................................................................................... 10 master mode ............................................................................................. 10 slave mode ............................................................................................... 10 analog connections .................................................................................. 10 high pass filter ........................................................................................ 11 power-up and calibration ......................................................................... 11 synchronization of multiple devices ......................................................... 12 grounding and power supply decoupling ................................................ 12 performance ............................................................................................... 12 digital filter ............................................................................................... 12 pin descriptions ......................................................................................... 14 parameter definitions ............................................................................. 18 references ................................................................................................... 19 package dimensions .................................................................................. 20
cs5394 ds258pp4 3 analog characteristics (t a = 25 c; va, vl, vd = 5 v; full-scale input sinewave, 997 hz; fs = 48 khz; sclk = 3.072 mhz; analog connections as shown in figure 1; measurement bandwidth is 20 hz to 20 khz unless otherwise specified; logic 0 = 0 v, logic 1 = vd.) notes: 1. referenced to typical full-scale differential input voltage (4.0 vpp). 2. specified for a fully differential input {(ainr+) - (ainr-)}. full-scale outputs will be produced for differential inputs beyond v in and within va and agnd. * refer to parameter definitions at the end of this data sheet. specifications are subject to change without notice parameter symbol min typ max unit dynamic performance dynamic range a-weighted tbd tbd 114 117 - - db total harmonic distortion + noise (note 1) -1.0 db -20 db -60 db thd+n - - - -103 -94 -54 tbd tbd tbd db total harmonic distortion -1.0 db (note 1) thd - 0.0007 tbd % interchannel phase deviation - 0.01 - degree interchannel isolation - 118 - db dc accuracy interchannel gain mismatch - 0.05 - db gain error - 5 tbd % gain drift - 100 - ppm/c bipolar offset error with high pass filter - 0 - lsb analog input full-scale differential input voltage (note 2) v in tbd 4.0 tbd v pp input impedance z in -4.5-k w common-mode rejection ratio cmrr - 82 - db common mode bias voltage vcom - 2.5 - v
cs5394 4 ds258pp4 power and thermal characteristics (t a = 25 c; va, vl, vd = 5 v 5%; fs = 48 khz; master mode.) digital filter characteristics (t a = 25 c; va, vl, vd = 5 v 5%; fs = 48 khz) notes: 3. filter characteristic scales with sample rate. 4. the analog modulator samples the input at 3.072 mhz for fs equal to 48 khz. there is no rejection of input signals which are (n 3.072 mhz) 22.1 khz, where n = 0, 1, 2, 3, ... digital characteristics (t a = 25 c; va, vl, vd = 5 v 5%) parameter symbol min typ max unit power supply current (normal operation) (va) + (vl) vd i a i d - - 85 65 tbd tbd ma ma power supply current (power-down mode) (va) + (vl) vd i a i d - - 2 2 - - ma ma power consumption normal operation power-down mode - - 750 20 tbd - mw mw power supply rejection ratio 1 khz psrr - 65 - db allowable junction temperature - - 135 c junction to ambient thermal impedance q ja -45-c/w parameter symbol min typ max unit passband -0.01 db (note 3) 0 - 22.1 khz passband ripple - - 0.005 db stopband (note 3) 26.6 - 3050 khz stopband attenuation (note 4) 117 - - db group delay (fs = output sample rate) t gd - 34/fs - s group delay variation vs frequency d t gd --0.0s high pass filter characteristics frequency response -3 db (note 3) -0.036 db - - 1.8 20 - - hz phase deviation @ 20 hz (note 3) - 5.3 - degree passband ripple - - 0 db parameter symbol min max unit high-level input voltage mclka/d only v ih 2.4 3.0 - - v v low-level input voltage mclka/d only v il - - 0.8 1.0 v v high-level output voltage v oh (vd) - 1.0 - v low-level output voltage v ol -0.4v input leakage current i in -10 m a
cs5394 ds258pp4 5 absolute maximum ratings (agnd, dgnd = 0 v, all voltages with respect to ground.) notes: 5. any pin except supplies. transient currents of up to 100 ma on the analog input pins will not cause scr latch-up. 6. the maximum over/under voltage is limited by the input current. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (agnd, dgnd = 0 v, all voltages with respect to ground.) parameter symbol min max unit dc power supplies positive analog positive logic positive digital |va - vd| |va - vl| |vd - vl| va vl vd -0.3 -0.3 -0.3 - - - +6.0 +6.0 +6.0 0.4 0.4 0.4 v input current (note 5) i in -10ma analog input voltage (note 6) v ina -0.7 (va) + 0.7 v digital input voltage (note 6) v ind -0.7 (vd) + 0.7 v ambient operating temperature (power applied) t a -55 +100 c storage temperature t stg -65 +150 c parameter symbol min typ max unit dc power supplies positive analog positive logic positive digital |va - vd| va vl vd 4.75 4.75 4.75 - 5.0 5.0 5.0 - 5.25 5.25 5.25 0.4 v
cs5394 6 ds258pp4 switching characteristics (t a = -10 to 70 c; va = vl = vd = 5 v 5%; inputs: logic 0 = 0 v , logic 1 = va = vl = vd; c l = 20 pf) notes: 7. 8. 9. parameter symbol min typ max unit output sample rate f s 2-50khz mclk period t clkw 78 - 1950 ns mclk low t clkl 26 - - ns mclk high t clkh 26 - - ns mclk fall time - - 12 ns master mode sclk falling to lrck t mslr -20 - +20 ns sclk falling to sdata valid t sdo --20ns sclk duty cycle - 50 - % slave mode lrck period 1/f s 20 - 500 s lrck duty cycle tbd 50 tbd % sclk period t sclkw (note 7) - - ns sclk pulse width low t sclkl (note 8) - - ns sclk pulse width high t sclkh 60 - - ns sclk falling to sdata valid t dss - - (note 9) ns lrck edge to msb valid t lrdss - - (note 9) ns sclk rising to lrck edge delay t slr1 (note 9) - - ns lrck edge to rising sclk setup time t slr2 (note 9) - - ns 1 128 f s ------------------ 1 256 f s ------------------ 1 512 f s ------------------ 2 0 +
cs5394 ds258pp4 7 sclk output t mslr sdata t sdo lrck output msb msb-1 sdata sclk input lrck input sclkl t dss t msb msb-1 sclkh t slr1 t slr2 t t sclkw sclk to sdata & lrck - master mode serial data format, dfs low sclk to lrck & sdata - slave mode serial data format, dfs low sclk to sdata & lrck - master mode serial data format, dfs high i 2 s compatible sclk to sdata & lrck - master mode serial data format, dfs high i 2 s compatible sclk output t mslr sdata t sdo lrck output msb sdata sclk input lrck input sclkl t dss t msb msb-1 msb-2 lrdss t sclkh t slr1 t slr2 t t sclkw
cs5394 8 ds258pp4 vref ainl+ ainl- tsto1 tsto2 vd 3.9nf 0.1 m f left analog input - left analog input + a/d converter sclk cs5394 s/m mclka ainr+ right analog input - ainr- right analog input + vcom 100 m f + ferrite bead may be used if vd is derived from va. if used, do not drive any other logic from vd. an example ferrite bead is permag vk200-2.5/52 tsto pins should be left floating, with no trace 39 w pdn adctl dactl va vl +5v analog 1 m f ferrite bead +5v digital 5.1 w 1 m f + + + 10 m f + sdata* agnd lgnd dgnd agnd 22 12 28 25 21 8 6 9 20 7 14 13 16 17 18 19 11 23 24 1 2 4 5 27 26 39 w 39 w 39 w 3.9nf mclkd dfs lrck dgnd 15 agnd 3 mode settings cal 10 power down and calibration control audio data processor timing logic and clock 0.1 m f 0.1 m f.1 m f 0.1 m f * refer to sdata pin description figure 1. typical connection diagram
cs5394 ds258pp4 9 general description the cs5394 is a 24-bit, stereo a/d converter de- signed for stereo digital audio applications. the de- vice uses a patented, 7th-order tri-level delta-sigma modulator to sample the analog input signals at 64 times the output sample rate (fs) of the device. sample rates of up to 50 khz are supported. the an- alog input channels are simultaneously sampled by separate delta-sigma modulators. the resulting se- rial bit streams are digitally filtered, yielding pairs of 24-bit values. this technique yields nearly ideal conversion performance independent of input fre- quency and amplitude. the converter does not re- quire difficult-to-design or expensive anti-alias filters and it does not require external sample-and- hold amplifiers or voltage references. an on-chip voltage reference provides for a differ- ential input signal range of 4.0 vpp. the device also contains a high pass filter, implemented digi- tally after the decimation filter, to completely elim- inate any internal offsets in the converter or any offsets present at the input to the device. output data is available in serial form, coded as 2's com- plement 24-bit numbers. for more information on delta-sigma modulation techniques see the references at the end of this data sheet. system design very few external components are required to sup- port the adc. normal power supply decoupling components, voltage reference bypass capacitors and a single resistor and capacitor on each input for isolation are all that's required, as shown in figure 1. master clock the master clock is the clock source for the delta- sigma modulator (mclka) and digital filters (mclkd). the required mclka/d frequencies are determined by the desired fs and must be 256x fs, as shown in table 1. serial data interface the cs5394 supports two serial data formats which are selected via the digital format select pin, dfs. the digital format determines the relation- ship between the serial data, left/right clock and se- rial clock. figures 2 and 3 detail the interface formats. the serial data interface is accomplished via the serial data output, sdata, serial data clock, sclk, and the left/right clock, lrck. the serial nature of the output data results in the left and right data words being read at different times. however, the samples within each left/right pair represent simultaneously sampled analog inputs. serial data the serial data block consists of 24 bits of audio data presented in 2's-complement format with the msb-first. the data is clocked from sdata by the serial clock and the channel is determined by the left/right clock. serial clock the serial clock shifts the digitized audio data from the internal data registers via the sdata pin. sclk is an output in master mode where internal dividers will divide the master clock by 4 to gener- ate a serial clock which is 64 fs. in slave mode, sclk is an input with a serial clock typically be- tween 48 and 128 fs. it is recommended that sclk be equal to 64 fs, though other frequencies are possible, to avoid potential interference effects which may degrade system performance. lrck (khz) mclka/d (mhz) sclk (mhz) 32 8.192 2.048 44.1 11.2896 2.822 48 12.288 3.072 table 1. common clock frequencies
cs5394 10 ds258pp4 left / right clock the left/right clock, lrck, determines which channel, left or right, is to be output on sdata. in master mode, lrck is an output whose frequency is equal to fs. in slave mode, lrck is an input whose frequency must be equal to fs and synchro- nous to mclka/d. master mode in master mode, sclk and lrck are outputs which are internally derived from the master clock. internal dividers will divide mclka/d by 4 to generate a sclk which is 64 fs and by 256 to generate a lrck which is equal to fs. the cs5394 is placed in the master mode with the slave/master pin, s/m , low. slave mode lrck and sclk become inputs in slave mode. lrck must be externally derived from mclka/d and be equal to fs. it is recommended that sclk be equal to 64 . other frequencies between 48 and 128 fs are possible but may degrade system performance due to interference effects. the mas- ter clock frequency must be 256 fs. the cs5394 is placed in the slave mode with the slave/master pin, s/m , high. analog connections figure 1 shows the analog input connections. the analog inputs are presented differentially to the modulators via the ainr+/- and ainl+/- pins. each analog input will accept a maximum of 2.0 vpp. the + and - input signals are 180 out of phase resulting in a differential input voltage of 4.0 vpp. figure 4 shows the input signal levels for sdata 23 22 7 6 23 22 sclk lrck 23 22 master 24-bit left justified data data valid on rising edge of 64x sclk mclk equal to 256x f s 54 32 10 8 76 54 32 10 8 9 9 slave 24-bit left justified data data valid on rising edge of sclk mclk equal to 256x f s left channel right channel figure 2. serial data format, dfs low sdata 23 22 8 7 23 22 sclk lrck 23 22 65 43 21 0 87 65 43 21 0 slave i s 24-bit data data valid on rising edge of sclk mclk equal to 256x f s 2 master i s 24-bit data data valid on rising edge of 64x sclk mclk equal to 256x f s 2 9 9 left channel right channel figure 3. serial data format, dfs high (i 2 s compatible)
cs5394 ds258pp4 11 full scale. input signals can be ac or dc coupled. the vcom output is available to filter the internal common mode and it is recommended that this out- put be used to bias the analog input buffer to mini- mize distortion. however, this pin is not intended to supply significant amounts of current and is sus- ceptable to noise coupling into the sampling cir- cuits. please refer to the CDB5394 for a suggested implementation. the cs5394 samples the analog inputs at 64 fs, 3.072 mhz for a 48 khz sample-rate. the digital filter rejects all noise above 26.6 khz except for frequencies at 3.072 mhz 22.1 khz (and multi- ples of 3.072 mhz). most audio signals do not have significant energy at 3.072 mhz. nevertheless, a 39 w resistor in series with each analog input and a 3.9 nf capacitor across the inputs will attenuate any noise energy at 3.072 mhz, in addition to provid- ing the optimum source impedance for the modula- tors. the use of capacitors which have a large voltage coefficient must be avoided since these will degrade signal linearity. npo and cog capacitors are recommended. if active circuitry precedes the adc, it is recommended that the above rc filter is placed between the active circuitry and the ainr and ainl pins. the above example frequencies scale linearly with sample rate. the on-chip voltage reference is available at vref for the purpose of decoupling only. the circuit traces attached to this pin must be minimal in length and no load current may be taken from vref. the recommended decoupling scheme, figure 1, is a 100 f electrolytic capacitor and a 0.1 f ceramic capacitor connected from vref to agnd. the decoupling capacitors, particularly the 0.1 f, must be positioned to minimize the electri- cal path from vref and pin 3, agnd, on the printed circuit board. high pass filter the cs5394 includes a high pass filter after the decimator to remove the indeterminate dc offsets introduced by the analog buffer stage and the cs5394 analog modulator. the first-order high pass filter are detailed in the digital filter specifi- cations table. the filter response scales linearly with sample rate. power-up and calibration reliable power-up can be accomplished by with- holding the mclka/d until the 5 volt power and configuration pins are stable. it is also recommend- ed that the mclka/d be removed if the supplies drop below 4.75 volt to prevent power glitch relat- ed issues. the delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either through the application of power or by exit- ing the power-down mode. however, the voltage reference will take much longer to reach a final val- ue due to the presence of external capacitance on the vref pin. a calibration of the tri-level delta-sigma modulator should always be initiated following power-up and after allowing sufficient time for the voltage on the external vref capacitor to settle. this is required to minimize noise and distortion. calibration is ac- tivated on a rising edge applied to the cal pin and requires 4100 lrck cycles. it is also advised that the cs5394 be calibrated after the device has reached thermal equilibrium to maximize perfor- mance. +3.5 v +2.5 v +1.5 v +3.5 v +2.5 v +1.5 v cs5394 ain+ ain- full scale input level= (ain+) - (ain-)= 4.0 vpp figure 4. full scale input voltage
cs5394 12 ds258pp4 synchronization of multiple devices in systems where multiple adcs are required, care must be taken to achieve simultaneous sampling. it is recommended that the rising edge of the cal signal be timed with a falling edge of mclk to en- sure that all devices will initiate a calibration and synchronization sequence on the same rising edge of mclk. the absence of re-timing of the cal signal can result in a sampling difference of one mclk period. grounding and power supply decoupling as with any high resolution converter, the adc re- quires careful attention to power supply and grounding arrangements if its potential perfor- mance is to be realized. figure 1 shows the recom- mended power arrangements, with va and vl connected to a clean +5 v supply. vd, which pow- ers the digital filter, may be run from the system +5 v logic supply. alternatively, vd may be pow- ered from the analog supply via a ferrite bead. in this case, no additional devices should be powered from vd. decoupling capacitors should be as near to the adc as possible, with the low value ceramic capacitor being the nearest. the printed circuit board layout should have sepa- rate analog and digital regions and ground planes, with the adc straddling the boundary. all signals, especially clocks, should be kept away from the vref pin in order to avoid unwanted coupling into the modulators. the vref decoupling capacitors, particularly the 0.1 f, must be positioned to mini- mize the electrical path from vref and pin 3, agnd. the CDB5394 evaluation board demon- strates the optimum layout and power supply ar- rangements, as well as allowing fast evaluation of the adc. to minimize digital noise, connect the adc digital outputs only to cmos inputs. performance digital filter figures 5-8 show the performance of the digital fil- ter included in the adc. all plots are normalized to fs. assuming a sample rate of 48 khz, the 0.5 frequency point on the plot refers to 24 khz. the filter frequency response scales precisely with fs.
cs5394 ds258pp4 13 figure 5. cs5394 stopband attenuation figure 6. cs5394 passband ripple figure 7. cs5394 transition band figure 8. cs5394 transition band
cs5394 14 ds258pp4 pin descriptions power supply connections va - analog power, pin 24. positive analog supply. nominally +5 volts. vl - logic power, pin 23. positive logic supply for the analog section. nominally +5 volts. agnd - analog ground, pins 3, 25, and 28. analog ground reference. lgnd - logic ground, pin 22. ground reference for the logic portions of the analog section. vd - digital power, pin 11. positive supply for the digital section. nominally +5 volts. dgnd - digital ground, pins 12 and 15. digital ground reference for the digital section. 1 2 3 4 5 6 7 821 22 23 24 25 26 27 28 agnd ainr+ ainr- agnd va vl lgnd tsto2 tsto1 mclka adctl ainl- ainl+ agnd vcom vref 9 10 11 12 17 18 19 20 mclkd pdn dfs s/m dgnd vd cal dactl 13 14 15 16 sdata dgnd sclk lrck test output analog section clock input analog control data input left channel analog input- left channel analog input+ analog ground common mode voltage output voltage reference digital ground digital section power calibration control data output serial clock left/right clock analog ground right channel analog input+ right channel analog input- analog ground positive analog power analog section logic power analog section logic ground test output digital section clock input power down serial data format select slave/master mode serial data output digital ground
cs5394 ds258pp4 15 analog inputs ainr-, ainr+ - differential right channel analog inputs, pins 26 and 27. analog input connections for the right channel differential inputs. nominally 4.0 vpp differential for full-scale digital output. ainl-, ainl+ - differential left channel analog inputs, pins 4 and 5. analog input connections for the left channel differential inputs. nominally 4.0 vpp differential for full-scale digital output. analog outputs vcom - common mode voltage output, pin 2. nominally +2.5 volts. requires a 10 m f electrolytic capacitor in parallel with 0.1 m f ceramic capacitor for decoupling to agnd. caution is required if this output be used to bias the analog input buffer circuits. refer to the CDB5394 as an example. vref - voltage reference output, pin 1. nominally +4 volts. requires a 100 m f electrolytic capacitor in parallel with 0.1 m f ceramic capacitor for decoupling to agnd. digital inputs adctl - analog control input, pin 6. must be connected to dactl. this signal enables communication between the analog and digital circuits. dfs - digital format select, pin 18. the relationship between lrck, sclk and sdata is controlled by the dfs pin. when high, the serial output data format is i 2 s compatible. the serial data format is left-justified when low. cal - calibration, pin 10. activates the calibration of the tri-level delta-sigma modulator on the rising edge of the cal input. mclka - analog section input clock, pin 7. this clock is internally divided and controls the delta-sigma modulators. an mclka frequency of 12.288 mhz sets a modulator sampling rate of 3.072 mhz and a output sample rate of 48 khz. mclka must be connected to mclkd.
cs5394 16 ds258pp4 mclkd - digital section input clock, pin 20. mclkd clocks the digital filter and must be connected to mclka. the required mclkd frequency is determined by the desired sample rate. a mclkd of 12.288mhz corresponds to fs equal to 48 khz. mclka must be connected to mclkd. pdn - power down, pin 19. when high, the device enters power down. upon returning low, the device enters normal operation and issues commands to initialize the voltage reference and synchronize the analog and digital sections of the device. s/m - slave or master mode, pin 17. when high, the device is configured for slave mode where lrck and sclk are inputs. the device is configured for master mode where lrck and sclk are outputs when s/m is low. digital outputs dactl- digital to analog control output, pin 9. must be connected to adctl. this signal enables communication between the digital and analog circuits. sdata - digital audio data output, pin 16. the 24-bit audio data is presented msb first, in 2's complement format. this pin has a internal pull-down resistor and must remain low during the power-up sequence to avoid accessing a test mode. digital inputs or outputs lrck - left/right clock, pin 13. lrck determines which channel, left or right, is to be output on sdata. the relationship between lrck, sclk and sdata is controlled by the digital format select (dfs) pin. although the outputs for each channel are transmitted at different times, left/right pairs represent simultaneously sampled analog inputs. in master mode, lrck is an output whose frequency is equal to fs. in slave mode, lrck is an input whose frequency must be equal to fs. sclk - serial data clock, pin 14. clocks the individual bits of the serial data from sdata. the relationship between lrck, sclk and sdata is controlled by the digital format select (dfs) pin. in master mode, sclk is an output clock at 64 fs. in slave mode, sclk is an input which requires a continuously supplied clock at any frequency from 48 to 128 fs (64 is recommended).
cs5394 ds258pp4 17 miscellaneous tsto1, tsto2 - test outputs, pins 8 and 21. these pins are intended for factory test outputs. they must not be connected to any external component or any length of circuit trace.
cs5394 18 ds258pp4 parameter definitions dynamic range the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise ratio measurement over the specified band width made with a -60 dbfs signal. 60 db is added to resulting measurement to refer the measurement to full-scale. this technique ensures that the distortion components are below the noise level and do not effect the measurement. this measurement technique has been accepted by the audio engineering society, aes17-1991, and the electronic industries association of japan, eiaj cp-307. expressed in decibels. total harmonic distortion + noise the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified band width (typically 10 hz to 20 khz), including distortion components. expressed in decibels. measured at -1 and -20 dbfs as suggested in aes17-1991 annex a. frequency response a measure of the amplitude response variation from 10 hz to 20 khz relative to the amplitude response at 1 khz. units in decibels. interchannel isolation a measure of crosstalk between the left and right channels. measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full-scale analog output for a full-scale digital input. gain drift the change in gain value with temperature. units in ppm/c. offset error the deviation of the mid-scale transition (111...111 to 000...000) from the ideal. units in mv.
cs5394 ds258pp4 19 references 1) "techniques to measure and maximize the performance of a 120 db, 96 khz a/d comveter integrated circuit by steven harris, steven green and ka leung. presented at the 103rd convention of the au- dio engineering society, september 1997. 2) "a stereo 16-bit delta-sigma a/d converter for digital audio" by d.r. welland, b.p. del signore, e.j. swanson, t. tanaka, k. hamashita, s. hara, k. takasuka. paper presented at the 85th convention of the audio engineering society, november 1988. 3) "the effects of sampling clock jitter on nyquist sampling analog-to-digital converters, and on oversampling delta sigma adc's" by steven harris. paper presented at the 87th convention of the audio engineering society, october 1989. 4) "an 18-bit dual-channel oversampling delta-sigma a/d converter, with 19-bit mono application example" by clif sanchez. paper presented at the 87th convention of the audio engineering society, october 1989. 5) "how to achieve optimum performance from delta-sigma a/d and d/a converters" by steven har- ris. presented at the 93rd convention of the audio engineering society, october 1992. 6) "a fifth-order delta-sigma modulator with 110db audio dynamic range" by i. fujimori, k. ha- mashita and e.j. swanson. paper presented at the 93rd convention of the audio engineering society, october 1992.
cs5394 20 ds258pp4 package dimensions inches millimeters dim min max min max a 0.093 0.104 2.35 2.65 a1 0.004 0.012 0.10 0.30 b 0.013 0.020 0.33 0.51 c 0.009 0.013 0.23 0.32 d 0.697 0.713 17.70 18.10 e 0.291 0.299 7.40 7.60 e 0.040 0.060 1.02 1.52 h 0.394 0.419 10.00 10.65 l 0.016 0.050 0.40 1.27 0 8 0 8 28l soic (300 mil body) package drawing d h e b a1 a c l seating plane 1 e
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